1. Related Patent Applications
“A Novel Monolithic, Combination Nonvolatile Memory Allowing Byte, Page a Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout ”, U.S. patent application Ser. No. 10/223,208, filed Aug. 19, 2002, assigned to the same assignee as the present invention, and herein incorporated by reference.
“A Novel Monolithic, Combination Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout”, U.S. patent application Ser. No. 10/351,180, filed Jan. 24, 2003, assigned to the same assignee as the present invention, and herein incorporated by reference.
“A Combination Nonvolatile Memory Using Unified technology with Byte, Page and Block Write and Simultaneous Read and Write Operations”, U.S. patent application Ser. No. 10/351,179, filed Jan. 24, 2003, assigned to the same assignee as the present invention, and herein incorporated by reference.
“A Novel Combination Nonvolatile Integrated Memory System Using a Universal Technology Most Suitable for High-Density, High-Flexibility And High-Security Sim-Card, Smart-Card And E-Passport Applications”, U.S. patent application Ser. No. 11/025,822, filed Dec. 24, 2004, assigned to the same assignee as the present invention, and herein incorporated by reference.
2. Field of the Invention
This invention relates generally to integrated circuit memory. More particularly this invention relates to combinations of volatile and nonvolatile memory incorporated with an integrated circuit structure. Even more particularly this invention relates to combinations of static random access memory (SRAM), NAND flash electrically erasable programmable read only memory (flash memory), and NAND configured electrically erasable programmable read only memory (EEPROM) on one substrate for incorporation with a system-on-a-chip structure (SOC).
3. Description of Related Art
Volatile memory, as is well known in the art, retains data temporarily such that that any interruption of the power supply voltage source causes a loss of the data. The static random access memory (SRAM) is well known example of a volatile memory and consists of a bistable transistor flip-flop or latching circuit. Referring to FIGS. 1a and 1b, the inverters I1 5 and I2 10 are coupled such that the output of the inverter I1 5 is connected to the input of the inverter I2 10 and the output of the inverters I2 10 is connected to the input of the inverter I1 5 to form the bistable latch. The access transistor Ma1 15 has a first source/drain terminal connected to the input of the inverter I1 5 and the output of the inverter I2 10 and a second source/drain terminal connected to the bit line BL 25. The access transistor Ma2 20 has a first source/drain terminal connected to the input of the inverter I2 10 and the output of the inverter I1 5 and a second source/drain terminal connected to the bit line BL 30. The gates of the access transistors Ma1 15 and Ma2 20 are connected to the word line WL 35 to receive the activation signals for accessing the memory cell.
In operation, the bit lines BL 25 and BL 30 are precharged respectively to the data to be written or read from the memory cell. The word Line WL 35 is set to a voltage level sufficient to activate the access transistors Ma1 15 and Ma2 20 and the digital signal representative of the binary data to be written to or read from the memory cell is transferred to or from the memory cell.
The inverter I1 5 consists of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 configured as the well known CMOS inverter. Similarly the inverter I2 10 consists of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 also configured a CMOS inverter. The gates of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the common drain connection of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 and the gates of the n-type MOS transistor Mn2 13 and the p-type MOS transistor Mp2 11 are connected to the common drain connection of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7. This forms the cross-connection to create the bistable flip-flop. The sources of the n-type MOS transistor Mn1 9 and the p-type MOS transistor Mp1 7 are connected to the ground reference voltage source and the sources of the p-type MOS transistors Mp1 7 and Mp2 11 are connected to the power supply voltage source VDD.
An alternative to the SRAM is a pseudo-static random access memory (PSRAM). The PSRAM is as is known in the art is formed of a single transistor gating charge representing the digital data to and from a capacitor. The structure is essentially that of a dynamic random access memory with the controls for refresh and timing being internally generated.
The alternative to the volatile memory is the nonvolatile read only memory (ROM). The cell structure and application of the nonvolatile ROM is well known in the art. The nonvolatile ROM has four classifications the masked Programmable Read Only Memory (ROM), Electrically Programmable Read Only Memory (EPROM), Erasable and Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable and Programmable Read Only Memory (Flash).
A masked ROM cell consists of a single transistor. The masked ROM cells are arranged in rows and columns. The gate of each ROM cell is connected to a word line, the drain is connected to a bit line and the source is connected to a source line. The programming or reprogramming of a ROM has to be performed during the integrated circuit fabrication through costly mask changes and a slow throughput of generally approximately one month. In a ROM array configuration, the ROM cells in each column are connected to a common bit line in parallel. Therefore, ROM read access speed is fast. A ROM cell uses a single polycrystalline silicon process on a P-type substrate. The mask programming of the ROM is performed using a post-polycrystalline silicon Boron implant that penetrates through the cell's polycrystalline silicon gate to channel to adjust the threshold voltage VT of the ROM cell.
The cell structure and application of the floating gate nonvolatile memories is well known in the art. The floating gate nonvolatile memory has three classifications the Electrically Programmable Read Only Memory (EPROM), Erasable and Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable and Programmable Read Only Memory (Flash). The EPROM is programmed by electrically forcing charge to the floating gate. Ultra-violet light is employed to eliminate (erase) the electrical charges of the programming from the floating gate of the EPROM. During EPROM program operation, in addition to a low-voltage power supply (VDD), an external high-voltage programming power supply (VPP) of about 12V is used. With a sealed package, UV-light cannot reach floating-gate, thus the erase operation is blocked and the EPROM is considered a One Time Programmable (OTP) EPROM. If the sealed OTP is changed to sealed Flash, then both erase and program operations can be performed electrically and repeatedly in system without the overheads of UV-light exposure and the external VPP programmer due to Flash's on-chip charge pump that can generate high voltage internally.
The sealed Flash is now able to be programmed and erased number times by using the external high-voltage power supplies to eliminate the on-chip charge pumps and state-machine without UV-light exposure to achieve numerous program and erase cycles. In this method, the die size can be drastically reduced for cost reduction. The prior art of the EEPROM and the Flash memories are structurally different at the individual cell as well as in technologies, array organizations and write schemes and conditions. In the prior art, 1-transistor NOR-type Flash, the drains of the cells within a block are connected in parallel to bit lines in cell array to achieve faster read speed. The erase block size is large ranging from 8 KB (64 Kb) to 64 KB (512 Kb) due to the limitation of erase operating voltage condition. The erase voltages have the memory cell's gate set to a voltage of approximately −10V and memory cell's P-Well set to approximately +10V. Having to set the P-Well to approximately +10V forces a requirement that the size of the sub-array or block of memory to be erased to be large to minimize the impact of the size constraints of a P-Well. Due to this operating voltage limitation, currently there is no page erase in unit of single word line size offered with acceptable endurance cycles of more than 100K in market. In the prior art, 1-transistor, NAND-type Flash memory, the drains and sources of cells are connected in series with a disadvantage of slower read speed but an advantage of most compact cell array. Like 1-transistor, NOR Flash, the cells are formed on P-well within deep N-well on top of P-substrate. The erase operation is performed by coupling the gate of the memory cell to the ground reference voltage (0V) and coupling the P-Well to a voltage source of approximately +20V. Having to apply the power supply to P-Well for each memory cell to be erased forces the erase size to be relatively large. The Erase size of the NOR flash memory cannot be performed in a unit of single word line. In prior art, typical 2-transistor EEPROM cell has cell scalability issue and stays at 0.25 μm.
The three nonvolatile memory technologies (EEPROM, NOR-type and NAND-type flash memory) of prior art are process incompatible and were never intended to be manufactured on a single integrated circuit chip. The EEPROM, NOR-type and NAND-type flash memory have the charge transferred to the floating gate for programming by either a channel hot injection (CHE) of the charge or by Fowler-Nordheim Tunneling (FN) through a tunneling oxide. The erasure of the EEPROM and Flash memory is generally by a Fowler-Nordheim Tunneling through the tunneling oxide.
Presently, the key primary applications nonvolatile memory systems and technologies are smart-cards. A smart card is a tiny secure computer processor embedded within a credit card-sized card. Smart cards presently are designed to comply with ISO/IEC 7816, 14443, and 15693 series of standards that define the physical shape of the smart card, the positions and shapes of its electrical connectors (if any), the communications protocols and power voltages to be applied to those connectors, the functionality, and the format of the commands sent to the card and the response returned by the card. Some smart cards may have physical connectors and other structures may have no external connections and communicate by way of radio frequency identification (RFID). Further, the compact nature of the smart card leads to the desirability for the processor, memory function, and support functions to be placed on a single chip.
The smart card is employed in such as applications Subscriber Identity Module (SIM-card) and Electronic Passport (e-passport to store personalized biometric data such as DNA, finger-print, iris and facial picture), to store data of multiple applications and Biometric Information Authentication System (BIAS) programs and to store small data such as telephone numbers and short email messages in same chip. Historically, the permanent program memory such as Basic Input/Output System (BIOS) and applications for the microprocessor was formed of classic mask programmable read only memory (ROM), and later as EPROM. Modifications to the program memory required physically changing the memory.
As the need to update the programs of the microprocessor and applications in system and allow for more than one time became more important, NOR-type flash memory was used. As the demand for serially downloading the audio and video slow-speed data, the high-density NAND-type flash was commonly used for cost reduction. But for those requiring byte-alterable small data memory, EEPROM was replacing flash memory. These three technologies were developed to provide in-system rewriteability. However, processes of EEPROM, NOR-type flash, NAND-type flash memories are not fully compatible in the present technology and are difficult to integrate on the same integrated circuit chip.
As the applications for microprocessors and microcontrollers are becoming more pervasive, the need for storage that is permanent and will not fail or disappear when power is removed is required. In most applications, the program is not modified often. However, the application data is changed relatively frequently. The program memory can be classified as configuration, traceablity, boot program, or main program and application programs. The application data includes information from any external input to the system, e.g., operational, instrument, recorder, or sensor data that is required for historical purposes or to maintain continuity of operation after power down or power loss. Data memory is typically frequently altered over the lifetime of the application, thus demand for much higher program/erase (P/E) cycles of more than 500K.
Recently, there are more and more applications that require addition of more security functions in smart card functions such as e-passport and SIM-card. Most of the security schemes are mandatory asking to store personalized biometric data such as DNA, iris, facial and finger prints. Traditionally, the small NAND-flash cell was not used in low-density card technology, thus the large NOR-type flash cell or the larger EEPROM cell were employed instead to store such biometric data. The effective cell size of 1-transistor NAND is around 4λ square, while 1-transistor NOR-type Flash is around 10λ square and 2-transistor EEPROM cell is about 80λ square. Please, note that λ is a unit of the minimum feature size. That means λ of a 0.13 μm process is 0.13 μm. Obviously, using the big 1-transisitor NOR Flash and the bigger EEPROM cell to store personalized biometric data is wasteful of space. Particularly, in smart card technology, the final die size of a smart card system-on-a-chip that contains all Flash, EEPROM, SRAM, CPU, and Cryptographic processor has to be made within 25 mm square to avoid die cracking. A system-on-a-chip (SOC) integrates all components of a computer system into a single chip. The chip contains an embedded computer processor, program memory, application data memory, and appropriate input/output function. In applications such as cellular telephones and wireless personal digital assistants, a SOC contains digital, analog, mixed-signal, and radio-frequency functions within a single integrated circuit chip
With higher and higher security required for smart card applications, the pressure of more and more personalized data is strongly required in a tiny die area of card. For example, storing ten finger prints is more preferable than to store just one thumbprint from security viewpoint. Having facial picture data from more angles is superior to the data from just one angle. Storing whole finger prints, iris and facial pictures or even DNA in one chip is better than to store part of it from security perspective.
The cells size of the EEPROM and NOR-type Flash memories no longer make these memories a cost effective solution to store personalized biometric data. The smallest cell size of 1-transistor NAND-type flash as noted above is 4λ square and is preferably used for personalized data storage memory.
High-level language software such as Java card system from Sun Microsystems, Inc., Santa Clara, Calif. 95054 provide easy and fast development software processes for creating and integrating software for multiple application down-loadable programs. Therefore, a flexible, easily partitioned small, non-uniform block size NOR-type flash system for multiple function programs is desirable in smart card applications.
The traditional large cell size of EEPROM technology is essentially non-scalable below 0.25 μm and thus it is not suitable for storing memory density higher than 1 Mb (128 KB). The trend is to use low-cost flash technology to replace traditional EEPROM but still retain the features of byte-alterable scheme and high PIE cycles of more than 500K.
The number of times that a nonvolatile memory must be altered determines the endurance requirement of the device. Nonvolatility requires the device to retain data without power applied for the lifetime of the application. The lifetime of the application determines the data retention requirement of the device. Both of the reliability requirements of endurance and data retention have associated failure rates, which must be minimized. Since NOR-type flash memories is employed as the program and application memory, it has the less amount of reprogramming and erasing, therefore, it must have the longest data retention and require the medium endurance (approximately 100,000 program/erase cycles). Conversely, the EEPROM, employed as data memory, must be able to be modified repeatedly and therefore must have higher endurance (more than 1 million program and erase cycles). The NAND-type flash nonvolatile memory preferably used to store personalized data. It does not require too many updates and endurance (approximately 10K program/erase less cycles depending on the applications).
U.S. Pat. Nos. 6,801,458 and 6,370,081 (Sakui, et al.) provide a memory cell array that has a unit memory circuit formed from one memory cell and two select transistors sandwiching the memory cell. One block has one control gate line. Memory cells connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After data are superscribed on data in the sense amplifiers, and a page erase is performed, data in the sense amplifiers are programmed in the memory cells of one page. Superscription of data in the sense amplifiers allows a data change operation for byte data or page data. Sakui, et al. provides essentially 3-transistor EEPROM cell based on the structure of NAND cell. Each block of the EEPROM cells are grouped together in the individual wells such that the bulk of each memory cell of the block is commonly connected.